| 摘要 |
A buffer control circuit for a data processor which includes an operand buffer for storing operand data, and an instruction buffer for storing prefetched instruction data. The buffer control circuit includes a writing section and an outputting section. When an instruction decode signal is a branch instruction, the writing section reads out instruction data at a branch destination from a main memory and writes the instruction data in the operand buffer. When satisfaction of a condition of the branch instruction is signaled, the outputting section reads out the instruction data at the branch destination written in the operand buffer by the writing section and outputs the instruction data to an operating unit.
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