| 摘要 |
PURPOSE:To make infinite the number of peripheral devices which can be connected in series, by connecting the peripheral devices one after another in the order of higher priority, and controlling the permission or inhibition of the production of interruption to the peripheral device with lower priority. CONSTITUTION:When a cause to interruption request is produced at a peripheral device 21 and an interruption request flag 213 is set, an interruption request signal 6 when an interruption-enable input signal line (IE) 81 is on, is output and IE82 is off. Next, when CPU1 receives an interruption request, an interruption response signal 40 is output. This signal passes through the peripheral device 20 and is fed to the peripheral device 21, and the content of the vector address register 211 is output to the system bus 5 by setting the interruption reception flag 212 and making off the interruption request signal 6. |
