| 摘要 |
A power shutdown sequence provides for an orderly power shutdown for master and slave processors sharing a single power supply while at the same time allowing the master and slave processors to retain all the information learned regardless of failures. If the master senses a shutdown condition, it sends the slaves a power down signal confirming its intention to power down the system and commanding the slaves to initiate shutdown procedures, including the storing of variables to memory. In addition, the master also initiates shutdown procedures, and after a minimum time determined sufficient to allow the slave to complete their shutdown procedures, the master powers down the system. The slaves may also initiate their own powerdown procedures if a failure in the communications link with the master is sensed. |
