发明名称 SIGNAL SCRAMBLE SYSTEM
摘要 PURPOSE:To make the memory small in its capacity by giving an optional load value to an address counter and randomizing load values so as to rearrange the data in the signal scramble circuit in which the memory is controlled so as to decode the original data. CONSTITUTION:An input terminal 101 receiving a data to be sent is connected to memories 103,105 with a data capacity by one horizontal period via a switch 102. The memories 103,105 are selected for each horizontal period, to which a write address or a read address is given. While the memory 103 is for a write period, an address from an address converter 107 is given to the memory 103 and when the memory 103 is for a read period, an address from a horizontal counter 109 is given to the memory 103. Moreover, an address is given similarly even to the memory 105 and a data read from the memory is selected alternately for each horizontal period and the selected data is inputted to an input terminal 113 for a decoder side as a scrambled data.
申请公布号 JPH04273688(A) 申请公布日期 1992.09.29
申请号 JP19910034564 申请日期 1991.02.28
申请人 TOSHIBA CORP;TOSHIBA AVE CORP 发明人 IKEGAMI KIYOSHI
分类号 H04K1/04;G06F21/10;H04L9/34;H04N7/16;H04N7/167;H04N7/169 主分类号 H04K1/04
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