| 摘要 |
A wafer scale integration device comprises a plurality of real chips (2R1,2R2) formed in the center portion of a wafer (1) and a plurality of dummy chips (2D) formed in the circumference of the wafer (1). The dummy chips (2D) only include relay pads (7), some of the relay pads (7) are used for relaying bonding wires of power supply lines (4). Consequently, the power supply lines (4) do not short-circuit at edge portions of the wafer (1), since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad (7) connected to the bonding wire. |
