| 摘要 |
The bit error rate (BER) detection circuit detects the error contained in digital signal transmitted as form of alternate mark inversion code and generates error signal when error rate exceeds a limit. The circuit includes a JK flip flop for latching the signals transmitted through a first line (13) and a second line (15), a multipliers (14,16) for multiplying the latch output to the line data LINE (+), LINE(-), a multiplier (18) for multiplying inverted output signals of the multipliers (14,16), an error detector for detecting the error pulse by receiving a first duration and a second duration logic signal, and an error limit alarm signal generator (26) for generating error pulse signal when a second error occurs during the error duration limit.
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