| 摘要 |
PURPOSE:To enable combining in a system and generating PLL slip imperatively by providing a first frequency dividing circuit with variable frequency division ratio. CONSTITUTION:By changing the initialization value of a frequency division counter constituting a first frequency division circuit, the frequency division ratio changes and following to this, the frequencies of two clocks mCLK and sCLK for phase comparison object change and PLL slip is generated. This PLL slip is detected with an error detection circuit 4. By this, PLL slip is generated imperatively and the inspection of status accompanying an error due to the generation of the PLL slip and the inspection of the function of the error detection circuit 4, etc., are automatically done. |
