| 摘要 |
This invention refers to memories and digital telecommunications transmission. The invention concerns a method and a device for writing data into a memory FIFO and reading data from the memory in such a way that the rate of reading is on average the same as the rate of writing into the memory. Frames Datain arrive at the memory which comprise data information DATAINFOin and other information OTHER. Only the data information is to be written into the memory. A write-address generator WADRGEN generates a write address in a cyclic sequence for each arriving unit of data information which is to be written into the memory. For the reading from the memory the read addresses are generated in a read address generator RADRGEN in cyclic sequence. A phase locking circuit PLL can regulate the rate of reading by regulating the rate of generating the read addresses. According to the invention a situation where more or fewer units of data information than the nominal amount come into the memory FIFO in a frame is detected. If more or fewer units of data information come into the memory this is concealed initially from the phase locking circuit by a change in the first reference address a so that the phase locking circuit PLL momentarily does not change the rate at which the read addresses are generated. The concealment is thereafter removed step by step so that the phase locking circuit regulates the rate of generating the read addresses, that is the reading rate, step by step. The phase locking circuit is thereby not required to carry out very large changes in the rate quickly. <IMAGE> |
