| 摘要 |
<p>PURPOSE:To achieve that the delay time of clock signals supplied to a plurality of elements arranged on a semiconductor substrate or the like is made equal for all the elements. CONSTITUTION:Clusters 3 to 8 which have united two elements are formed. The clusters 3 and 4, 5 and 6, 7 and 8 are united; they are connected by clock signal lines 11, 12, 13. Branch points 01 to 03, on the clock signal lines 11, 12, 13, in which the delay time to both clusters becomes equal are found by taking into consideration the capacitance of the clusters as well as the wiring capacitance and the wiring resistance of the clock signal lines. The branch points 01 to 03 are connected by a clock signal line 14, and a branch point 04 is found. In addition, the branch points 02 and 04 are connected by a clock signal line 15, and a branch point 05 is found. The branch point 05 which has become finally one is connected to a root driver cell 2.</p> |
