| 摘要 |
PURPOSE:To reduce the size of a memory cell and to reduce the number of production processes in a semiconductor integrated circuit device which is provided with a vertical-structure mask ROM, an EPROM or an EEPROM. CONSTITUTION:The following are formed: a first-layer gate electrode 13 for a first memory cell QM at a vertical-structure mask ROM part 3 in a semiconductor integrated circuit device; and a second-layer gate electrode 17 for a second memory cell QM. The following are formed: a floating gate electrode 13 for a memory cell QEM at an EPROM part 4; and a control gate electrode 17. In addition, a source region and a drain region (an n-type semiconductor region 15 for the memory cell QEM is formed at the information write process of the second memory cell QM. |
