| 摘要 |
PURPOSE:To offer a timing generator which never causes dead time and besides, can change timing at any time. CONSTITUTION:A coarse timing pulse generating means (counter) 1 generates a coarse timing pulse for a desired timing by specifying properly an input clock pulse, and a timing vernier 2 generates a close timing pulse by delaying properly this coarse timing pulse. In a compensation circuit 4, the close timing pulse is inputted to a one-input plural-output delay circuit 41, and the output from its plural delayed outputs is selected by a multiplexer 42. Thus, while the multiplexer 42 outputs the output whose delay time is other than '0', the compensation circuit 4 can input the next pulse from the timing vernier 2, and the dead time is never caused. |
