| 摘要 |
<p>A readout column gate (23) comprises two [2] nMOS transistors (24,25). These nMOS transistors (24,25) connect with corresponding bit lines (BL,BLX) at their respective gates, with corresponding data buses (DB,DBX) at their respective drains, and with common readout column selection line (CLR) at their respective sources. The column driver sets the voltage of the readout column selection line (CLR) to a voltage different than the voltage precharged to the bit lines (BL,BLX) when a column is selected. The improved readout column gate (23) expedites a DRAM access without incurring an increase in the size of a chip area. <IMAGE></p> |
