| 摘要 |
A serial binary multiplier receives a multiplicand and a multiplier, and produces a product. The multiplicand is received in a serial format beginning with a most significant bit and ending with a least significant bit. The multiplier is received in a parallel format, and the product is available in both serial and parallel formats. The multiplier consists of a multiples generator, an arithmetic unit, and a decoder. The multiples generator generates a multiple of the multiplicand for each bit of the multiplier that is equal to logic one. The multiples generator produces the multiples in a serial format beginning with a most significant bit and ending with a least significant bit. The arithmetic unit serially receives the multiples produced by the multiples generator, and produces the sum of the multiples. The sum is produced in the form of two serial binary numbers which compose an unsigned redundant binary number. The decoder receives the unsigned redundant binary number produced by the arithmetic unit. The decoder converts the unsigned redundant binary number into a conventional binary number which represents the product of the multiplicand and the multiplier. The product is available in a parallel format, and in a serial format beginning with a most significant bit and ending with a least significant bit.
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