| 摘要 |
A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead of signalling exceptional conditions in terms of the event, e.g., "cache miss", exceptional conditions are signalled within the processor by deasserting the LoadX signals required by that exception. When the pipeline control for one pipestage is deasserted, in order to prevent previous instructions from entering the stalled pipestage, the detector of the exceptional condition must deassert all LoadX control signals for stages previous to X as well. |
