| 摘要 |
In a matrix array of registers, each register includes a latch having first and second terminals. First and second write transfer gates are responsive to a potential at a write address line for establishing a path from a first write data line to the first terminal of the latch and a path from a second write data line to the second terminal of the latch. A first junction is formed between series-connected N-channel MOS transistors whose gates are respectively coupled to the first and second terminals of the latch, and a second junction is likewise formed between series-connected N-channel MOS transistors whose gates are respectively coupled to the first and second terminals of the latch. First and second read transfer gates are respectively formed by N-channel MOS transistors which are responsive to a potential at a read address line for establishing a path from the first junction to a first read data line and a path from the second junction to a second read data line.
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