| 摘要 |
A synchronous, interleaved, time-division 1:M demultiplexor uses M equally-spaced phases of a clock signal having a frequency of B/M to latch M incoming serial data bits (where B is the incoming bit rate and M is an integer power of two equal to or greater than four). Following an input stage of parallel synchronous latches, an intermediate stage of parallel synchronous latches is used in which the intermediate latches are clocked with selected phases of the M-phase clock to latch each bit at a time at least 2/B (i.e., two incoming bit periods) after such bit is received from its respective input latch. Following the intermediate stage of parallel synchronous latches, an output stage of parallel synchronous latches is used in which the output latches are clocked with at least one selected phase of the M-phase clock to latch each bit at a time at least 2/B after such bit is received from its respective intermediate latch.
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