Semiconductor integrated circuit device comprising scan paths having individual controllable bypasses

摘要

Three shift path circuits (10', 20', 30') each comprising a bypass circuit are connected in series between a test data input (TDI) and a test data output (TDO). Each shift path circuit constitutes a design definition test data register connected to a circuit to be tested. Design modification of a testing circuit can be minimized by selectively operating the bypass circuit provided in a shift path circuit, even if there is circuit modification in the circuit to be tested. The period of time required for testing circuits to be tested is reduced.