| 摘要 |
PURPOSE:To prevent the collision on address and data buses, by executing the transfer of processor of the 2nd system, through receiving the permission of the direct access memory control section (DMA) after the execution of data transfer of the 1st system with priority. CONSTITUTION:The B address of the system B and B data buses 29, 30 are coupled with a B processor 9, B adaptor group 11 and B memory 12, and an A processor 5 of the system A, A memory 6 and A adaptor group 7 are connected to buses 29-30 via a bus control section 8'. Further, an address A and A data buses 27, 28 are coupled with the memory 6 and adaptor group 7 and connected to the processor 5 via the control section 8'. This control section 8' is provided with a bus control circuit 21 which controls the signal reception between the DMA control section 10 of the system B and the section 8'. Further, the data transfer of the processor 5 of the system A is executed with priority, and the data transfer of the processor 6 of the system B is executed after the reception of permission of the control section 10, to prevent the collision on the buses 27-30. |
