发明名称 SELECTION METHOD OF RETIMING SIGNAL EXTRACTION METHOD OF RETIMING SIGNAL AND GENERATION APPARATUS OF RETIMING SIGNAL
摘要 <p>PURPOSE: To realize accurate data retiming by selecting a retiming signal for a received serial data stream from plural local clock signals different in phase. CONSTITUTION: The indications of approximate time positions of data edge transitions related to DPLL local clocks, generated by a generator 14 are transferred from a data edge sorting circuit 30 in a digital phase-locked loop front end circuit 15 to the corresponding number of time slot counters 32 in a circuit 20 through a line 19. This counter block 32 includes a total counter and outputs a signal to a clock selecting logic 38 through a line 35. When a predetermined number of data transitions occur, that is, when they are counted by time slot counters, the total counter instructs this.</p>
申请公布号 JPH04264838(A) 申请公布日期 1992.09.21
申请号 JP19910270550 申请日期 1991.09.24
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 FURANKU DEEBITSUDO FUERAIORO;JIYON EDOUIN GERUSUBATSUHA;IRIYA YOSEFUOBITSUCHI NOBUOFU
分类号 H04L7/02;H04L7/033 主分类号 H04L7/02
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