| 摘要 |
<p>PURPOSE:To decrease wiring resistances of a gate line and a capacity line by opening a first contact hole at a silicon dioxide layer to form a metal layer, and so etching that the metal layer remains only on the gate line and the capacity line. CONSTITUTION:A first contact hole for removing lead wires from source and drain regions is opened at a first silicon dioxide layer by wet etching using etchant of fluoric acid series. Metal is so formed as to remain only on a gate line 105a and a capacitor line 106a, and wiring resistances of the gate line and the capacity line are reduced. A second contact hole is opened at a second silicon dioxide layer 108 by wet etching, etc., using etchant of fluoric acid series so as to obtain lead wires from source, drain region 101 and a gate electrode 104.</p> |
