发明名称 |
VARIABLE SELF-CALIBRATING DIGITAL DELAY CIRCUIT |
摘要 |
PURPOSE: To facilitate delay adjustment by converting an electric signal into the number of pulses and comparing this number of pulses with a second number defined by a user. CONSTITUTION: The waveform of an external oscillator is inputted to a selection circuit 101 through a line 52. It is gated by two additional inputs. That is, a line 51 as the output of a scan-in shift register 103 suggests whether or not delay data inputted by a user is properly inputted to the scan-in shift register 103, and a delay enable line 53 as a second input suggests whether or not delay adjustment is requested. When both inputs reach proper logical levels, the waveform given by the external oscillator in the selection circuit 101 is inputted to a controller 102. |
申请公布号 |
JPH04264810(A) |
申请公布日期 |
1992.09.21 |
申请号 |
JP19910270554 |
申请日期 |
1991.09.24 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
FURANSHISU ANTONII DERIRU;ARUFURETSUDO MIKAERU JIYAKUUTOTSUTO |
分类号 |
H03K5/00;H03K5/13;H03K5/135;H03K19/003 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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