| 摘要 |
PURPOSE:To realize the A/D converter able to obtain a clock synchronously with a timing at a high speed by revising a sampling timing in the A/D conversion over a wide range and controlling the delete of an operating reference clock for A/D conversion in response to a phase error in the reception operating timing and a modulation timing even when the A/D converter is applied to, e.g. a MODEM. CONSTITUTION:A variable frequency divider 116 frequency-divides a reference clock from an oscillator 117 according to a setting value of a frequency division ratio setting section 115 and sends the frequency division output to a clock delete section 119. The clock delete section 119 deletes the frequency division clock according to the delete of the clock set in response to a timing phase error between the modulation timing and the reception operating timing from a clock delete quantity setting section 120 to control an operating reference clock for A/D conversion thereby obtaining a clock in timing synchronization at a high speed. |
