| 摘要 |
PURPOSE: To attain additional propagation time regardless of wiring and to exclude hold time infringement through a simple means by providing a multiplexer connected to the output side behind a flip-flop consistuting a shift register. CONSTITUTION: A multiplexer M is provided behind a flip-flop FF, and a data output terminal QL of the FF is connected to a data input terminal '-1' of the multiplexer M. A data input terminal '1' of the multiplexer M is connected with a data input terminal B1, and a control input terminal G is connected with a control terminal B. Besides, a complementary output terminal QM or, the inverse of QM of the multiplexer M is connected to an output terminal Y or, the inverse of Y and complementary output terminals Q and Q of the FF are connected to output terminals X and, the inverse of X. Thus, the logical operation such as AND, OR or EXOR between the data of a terminal A and the data of a terminal B is possible. Thus, the additional propagation time becomes regardless of wiring and there is no hold time infringement. |
