| 摘要 |
PURPOSE:To shorten the delay time of a digit matching processing in an addition/subtraction high speed digit matching circuit. CONSTITUTION:A digit matching shifter 2 shifts a mantissa 200 of an operand to be subjected to digit matching in accordance with lower bit output data 111 of a digit matching quantity calculating adder 1 which makes a quick definite decision of data. A digit matching shifter 3 shifts digit matching intermediate result data 201 from the digit matching shifter 2 in accordance with upper bit output data 110 of the digit matching quantity calculating adder 1 which makes a slow definite decision of data. |
