发明名称 PHASE SYNCHRONIZING LOOP SYNTHESIZER
摘要 PURPOSE:To reduce the power consumption, to suppress the occurrence of noise other than a desired frequency due to the operation of a direct digital synthesizer, and to perform switching at a high speed. CONSTITUTION:A control signal to operate a direct digital synthesizer 11 for a prescribed time is inputted from a control signal input terminal 17 synchronously with the time slot transmitted or received by a radio machine. An analog switch 13 validates its output based on this control signal, and the direct digital synthesizer 11 is operated for the prescribed time based on this control signal.
申请公布号 JPH04260219(A) 申请公布日期 1992.09.16
申请号 JP19910042738 申请日期 1991.02.14
申请人 NEC CORP 发明人 FUJIWARA RYUHEI
分类号 H03L7/199;H03B28/00;H03L7/14;H03L7/16;H03L7/18 主分类号 H03L7/199
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