Pipelined multi-stage data processor including an operand bypass mechanism

摘要

A pipelined multi-stage data processor has a bypass circuit which is enabled when a memory reading request signal from the operand fetch stage and a memory writing request signal from the execution stage are simultaneously received by a control device with respect to an identical location in the memory. The bypass circuit operates to cause the write data to be written into the memory to be directly transferred to the fetch stage so that the memory reading operation is performed without actually accessing the memory.