CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY

摘要

PURPOSE:To provide a clock generating circuit which realizes a high speed cycle test of a semiconductor memory with a simple device. CONSTITUTION:Input/output latches 8 and 9, which make up the input/output section of a semiconductor memory, are controlled by a complementary clock. In order to make up complementary clocks CLKA and CLKB, an emitter follower circuit 6, which is OR-connected to a dummy terminal 7 and a differential amplifing circuit 3, is provided and by varying the cycle of output clock, a high speed cycle test of the semiconductor memory is realized.