| 摘要 |
PURPOSE:To make a system stable and reliable by limiting the amplitude of output signals of a data output buffer and suppressing noise induced by a Bi.CMOS dynamic RAM, etc., through a large fluctuation of a power source voltage. CONSTITUTION:A voltage limiter circuit VL contains MOSFETs Q11-Q13 which are arranged in series between the power source voltage VCC and the earth potential of the circuit. Among them, FET Q11 is constantly switched on as the gate is at the ground potential. FET Q11-Q13 turn to a diode form as the gate and drain is connected. The voltage of the commonly connected drain of FET Q1 and Q11 is supplied to the data output buffers DOB0-DOB3 as the output power source voltage VOL. Thus, when the absolute value of the voltage VCC is smaller than the resultant threshold value VTH of FET Q11-Q13, the output VOL is equal to the voltage VCC, and when VCC exceeds VTH, it is clamped at the potential of this resultant threshold value. |
