| 摘要 |
PURPOSE:To reduce the size of a memory cell. CONSTITUTION:A diffusion layer for a storage node part (n<+> type diffusion layer 6 which is a drain region of a transfer transistor T1, as cited as an example in the Figure) and a gate electrode (polycrystalline silicon layer 3 which is a gate electrode of a driving transistor Q1, as cited as an example in the Figure) are connected through a crystalline silicon layer 7 which is formed by the selection growth method. A source region of the driving transistor (n<+> type diffusion layer 6) and a ground potential interconnection 9 are also connected through the crystalline silicon layer 7 which is formed by the selection growth method. |
