Signal processor for mobile radio telephones - has interrupt address control to allow switch from main programme to interrupt routine with return at end

摘要

A digital radio telephone has a microphone output coupled to an A/D providing digital data for a signal processor that has an address unit coupled to a bus with an arithmetic logic unit, control unit, memories and programme module. The address unit contains a register module (29) and a decoder (37). The decoder operates in dependence upon the programme cycle or on the generation of an interrupt cycle. The address register has a main address stage (30) and a shadow address stage (31). Following an interrupt the decoder enables the shadow stage to store start address of the interrupt cycle. At the end of the cycle the contents are accessed and decoded and a return to the main programme occurs. ADVANTAGE - Interrupt processing requires min. time.