Electrically-erasable programmable read=only memory - has transistors holding unselected lines at given potential during data read=out

摘要

The memory has a number of bit lines (BLo,BL1...) selected in dependence on the received input address and intersecting word lines (WLo,WLi...), with the memory cells (MC) at their intersection points. Each bit line (BLo,BL1...)( is coupled to a read amplifier (S/AO,S/A1...) for the data obtained from the selected memory cell, the non-selected bit lines fixed at a given potential, during the read-out operation via read-out transistors (Q01,Q11...). The control signals for the latter transistors (Q01,Q11...) are determined from the read-out address information. ADVANTAGE - Reduced capacitive coupling between bit lines.