发明名称 PLANAR PROCESS UTILIZING THREE RESIST LAYERS
摘要 PURPOSE: To provide a planarization process employing three resist layers. CONSTITUTION: After forming a CVD oxide layer on a basic layer having trenches or steps of specified height separated by a variable distance on the surface thereof, a first resist layer is formed in a wide trench. A second resist layer is formed in order to increase and totally planarize the basic layer and then it is etched back until the resist is removed entirely from the active region thereof. Subsequently, a third resist layer is formed on the basic layer in order to provide a substantially planar surface. Finally, the resist and the CVD oxide are removed entirely from the active region.
申请公布号 JPH04253322(A) 申请公布日期 1992.09.09
申请号 JP19910159192 申请日期 1991.06.29
申请人 DIGITAL EQUIP CORP <DEC> 发明人 JIYON PII SUKUUPO;FURANSHISU PII ARUBUAREIZU;GUREGORII JIEI GURUURA
分类号 G03F7/26;H01L21/027;H01L21/3105;H01L21/3205;H01L21/762 主分类号 G03F7/26
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