发明名称 |
METHOD FOR FORMING VIAHOLE OF MULTILAYER CIRCUIT BOARD BY MACHINING |
摘要 |
PURPOSE:To improve the reliability of connection of a plated layer in a viahole formed in a multilayer circuit board by machining with an inner layer circuit. CONSTITUTION:A drill bit 4 is fed from above of the surface of a multilayer circuit board 1 to a position immediately before an inner layer circuit 2 to drill a guide hole 5, and then the bottom of the hole 5 is so flatly ground by a grindstone 6 formed at its end face in a flat surface as to arrive at the layer 2 to open an unpenetrating viahole 3 from the surface to the layer 2. The layer 2 can be exposed in a wide area in the bottom of the viahole 3 formed flatly by the grinding of the grindstone 6, and the contact area of a plated layer 7 provided in the viahole 3 with the circuit 2 can be increased. |
申请公布号 |
JPH04252096(A) |
申请公布日期 |
1992.09.08 |
申请号 |
JP19910008147 |
申请日期 |
1991.01.28 |
申请人 |
MATSUSHITA ELECTRIC WORKS LTD |
发明人 |
USAGAWA MICHINOBU;FUJIMORI SHOICHI;NOBETANI TORU |
分类号 |
H05K3/46;H05K3/00 |
主分类号 |
H05K3/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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