发明名称 DELAY CIRCUIT
摘要 PURPOSE:To realize delay attachment in which dispersion between the chips of a delay circuit formed on a semiconductor substrate can be remarkably suppressed. CONSTITUTION:A unit time signal with time width T is inputted to a first selection circuit 2. Delay is applied to (n) delay elements 1-1 to 1-n comprising a delay element group one by one by such input. and the output of either the delay elements which supply desired delay quantity is selected at a second selection circuit 9. A counter circuit 5 monitors the output of each delay element, and counts only the output of same high level, and supplies it to a first memory circuit 6. The first memory circuit 6 inputs the unit time signal 4, and stores and outputs the output of the counter circuit 5 set at a high level at the timing of trailing edge of the signal. A second memory circuit stores the desired delay quantity as NT, and the second selection circuit 9 decides the output stage of the delay element representing the delay quantity of NT based on the output of the delay circuit which offers the time width T outputted from the first memory circuit 6 and information offered from the second memory circuit 7, and outputs an input signal from the delay element at the delay stage.
申请公布号 JPH04249915(A) 申请公布日期 1992.09.04
申请号 JP19910000374 申请日期 1991.01.08
申请人 NEC ENG LTD 发明人 YONEDA KAZUHIRO
分类号 H01L21/82;H01L21/822;H01L27/04;H03K5/13;H03K5/133 主分类号 H01L21/82
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