| 摘要 |
A digital multiplier comprises AND gates (G1-G25) in which each digit of the multiplicand is multiplied by each digit of the multiplier. The outputs of the AND gates represent partical products which are then arranged corresponding to each digit of the multiplier. The multiplier further comprises 1's counters (CT1-CT8) for receiving in parallel all partial products, except the least significant digit of the multiplier, and any carries propagated from an adjacent counter, and for counting the number of '1' in the resultant values. The 1's counters output of least significant bit as the final products, and propagate the remaining bits to the next 1's counter.
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