发明名称 ERROR DETECTION AND FAULT SEPARATING MECHANISM
摘要 PURPOSE: To efficiently execute error detection and fault separation by a single error control mechanism. CONSTITUTION: Generally, the error detection and fault separation mechanism requires individual capture latches for capturing respective errors (e.g. from a parity inspector or a time-out counter) in each occurrence of an error and a related mask latch for temporarily or permanently blocking the detection of succeeding errors. The invension is characterized by substituting a single error control mechanism 160 capable of setting up and resetting the error capture latches for the mask latch. A detected error is stored in each capture latch and the capture of succeeding errors is prevented until the mechanism 160 resets the latch.
申请公布号 JPH04245548(A) 申请公布日期 1992.09.02
申请号 JP19910222453 申请日期 1991.08.08
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 JIRU JIERUBUEE
分类号 G06F11/34;G06F11/00;G06F11/07 主分类号 G06F11/34
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