发明名称 METHOD FOR WIRING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To minimize the fluctuation of delay time in signal transmission and, at the same time, shorten the delay time as a whole. CONSTITUTION:In semiconductor integrated circuit having a six-layered wiring layer structure composed of the first layer in which gates are closely arranged, second layer 2 formed as a logical wiring layer, third layer 3, fourth layer 4, fifth layer 5, and sixth layer 6 formed as a power source layer, wiring is made in the longitudinal direction in the second and fourth layers 4 and transversal direction in the third and fifth layers 3 and 5 and the second layer 2 which is the lowest layer of the ordinary wiring layers, fifth layer 5 which is the highest layer of the ordinary wiring layers, or both layers 2 and 5 are used as the principal wiring layer which must be taken into account for the delay time in signal transmission.
申请公布号 JPH04245456(A) 申请公布日期 1992.09.02
申请号 JP19910010293 申请日期 1991.01.31
申请人 HITACHI LTD;HITACHI SOFTWARE ENG CO LTD 发明人 SUZUKI KATSUKI;ISHII TAKEMOTO;TANIGUCHI TOMIO
分类号 H01L27/118;G06F17/50;H01L21/768;H01L21/82;H01L23/522;H01L23/528 主分类号 H01L27/118
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