LOCAL INTERCONNECT FOR INTEGRATED CIRCUITS

摘要

A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.