| 摘要 |
<p>Disclosed is a multiplying circuit in which a pair of common-base transistors (13, 14) each having a small emitter area are inserted between the common emitter terminals of first and second differential amplifiers (1,2; 3,4), which amplify a signal input to an input terminal pair and are connected in such a way as to cancel out their outputs which correspond to the input signal, and the output terminal pairs of multiple third differential amplifiers (5,6; 7,8), which amplify a signal input to another input terminal pair and have a predetermined DC offset characteristic. <IMAGE></p> |
