发明名称 |
Insulated gate field effect transistor with high breakdown voltage |
摘要 |
An MIS FET has an off-set gate structure in which a gate electrode and a drain region. The drain region is formed of an n type impurity region of a high concentration and has a pn junction region provided between the drain region and the p type silicon substrate. Further, n type impurity regions of the low concentration are in contact with a part of a peripheral portion of the n type impurity regions of the high concentration. The n type impurity regions of the low concentration alleviate the concentration of the electric field near the drain region to increase the drain breakdown voltage. The pn junction region of the n type impurity region of the high concentration and the p type silicon substrate increases a junction capacitance of the entire drain region, increases a surge current discharged to the substrate side from the drain region for the surge breakdown to increase the surge withstanding amount.
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申请公布号 |
US5144389(A) |
申请公布日期 |
1992.09.01 |
申请号 |
US19900583384 |
申请日期 |
1990.09.17 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
NAKAMURA, MITSUYOSHI;MIYATA, KAZUAKI |
分类号 |
H01L21/336;H01L29/06;H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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