发明名称 LOGICAL SIMULATION METHOD
摘要 PURPOSE:To make a period of time for propagating signals from an element having a plurality of fanouts shortest by enhancing the parallelism of propagation of a plurality of signals. CONSTITUTION:A plural fanout element finding section 1 inputs circuit description to find an element having a plurality of fanouts. An additional presignal propagation time calculating section 2 calculates a period of time for signal propagation from a found element. An additional postsignal time calculating section 3 calculates a period of time for signal propagation from the found element, provided that a fanout split element is added between the found element and a fanout destination of the found element. A compare discriminating section 4 compares all of a set of propagation times for these signals to judge the number of fanout split elements to be added. A fanout split element adding section 5 adds an appropriate number of fanout split elements in to a relevant circuit. A connection change section 6 changes connection accompanied by the addition. An allocation section 7 allocates adding fanout split elements to different processors.
申请公布号 JPH04243482(A) 申请公布日期 1992.08.31
申请号 JP19910004118 申请日期 1991.01.18
申请人 NEC CORP 发明人 OKUBO ICHIRO
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
代理机构 代理人
主权项
地址