| 摘要 |
<p>PURPOSE:To decrease the frequency of a source oscillation clock used in the inside of a decoder by providing a means interpolating a read signal of a valid data read from a memory means and converting it into a consecutive data on the processing unit. CONSTITUTION:Write is implemented continuously at a rate of 32.4MHz the same as a sampling frequency of an input data to high speed write high speed read memories (FIFO memories) 110-112 and the read is implemented at a rate of 44.5MHz and read inhibit is implemented at a rate once per three times. The read and read inhibit control is implemented by a read enable signal RE. Then the read output data is a discontinuous signal, then in order to convert it into a continuous signal, each output data is respectively inputted to interpolation filters 116-118.</p> |
