APPARATUS FOR INTERRUPT BUS MATCHING ON MULTIPROCESSOR SYSTEM

摘要

The interrupt bus is for communicating asynchronous signals between modules of multiprocessor system. The unit includes an inerrupt requester (4) for sending interrupt transmission request signal of system module to a corresponding interrupt processor, interrupt processors (5,6) for sending interrupt signal to the corresponding module, an interrupt signal to the corresponding module, an interrupt arbiter (7) for arbitrating the usage of the interrupt bus, a first and a second interrupt requester register (8,10) for storing data of the interrupt requester, a first and a second interrupt processor register, and adaptors (12,13) for forming signal line among the interrupt requestor (4), the interrup processors (5,6) and the interrupt bus (3).