发明名称 Electronic counter circuit with zero quiescent current - uses C-FET flip=flops to circuit passive state current flow esp. for modulo counters
摘要 The main switching circuit (10) contains a bank of FET flip-flops (1-10) each comprising two diodes (11, 12), four resistors (13) and two FETs (14, 15) configured so that a transistor (14) conducts when the applied gate voltage is high, while another transistor (15) conducts when the applied gate voltage is low. When a pulse is applied to the impulse control circuit clocking line (q), the flip-flop (21) and associated AND (22) and NOT (23) gates provide alternate pulses on the AND gate output lines. If the initial flip-flop (1) of the main switching circuit is in a high state and a pulse is received by the gate of transistor (16), the gate of the other transistor (14) is made high via a diode (11), enabling the latter transistor (14) to conduct, connecting point (e) to the zero volt line (d). This causes the first transistor (15) to conduct, raising point (f) to a high state, thus changing the state of the flip-flop and enabling the circuit to count in Modulo-10. ADVANTAGE - Uses no current in quiescent state.
申请公布号 DE4041056(A1) 申请公布日期 1992.08.27
申请号 DE19904041056 申请日期 1990.12.20
申请人 MERKLE, PAUL, 7032 SINDELFINGEN, DE 发明人 DER ERFINDER WIRD NACHTRAEGLICH BENANNT
分类号 H03K23/72 主分类号 H03K23/72
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