| 摘要 |
<p>A phase difference signal generator (10) responds to two input signals (fv, fr) to generate two phase difference signals (Av, Ar) which rise at a time interval corresponding to the phase difference between the two input signals and fall at the same time. A lagging signal detector (15) detects a lagging one of the two phase difference signals and a pulse generator (17) responds to the detected output from the lagging signal detector (15) to generate an appendage pulse of a width larger than a predetermined width. The appendage pulse (Afr, Afv) is appended, by a pulse appending circuit (16), to each of the two phase difference signals to form an extended phase difference signal ( phi v, phi r). A phase difference detector (14) detects the difference between the two extended phase difference signals and outputs a low-frequency component of the difference as a voltage corresponding to the phase difference between the two input signals. <IMAGE></p> |
