| 摘要 |
<p>A duo-binary and/or binary data slicer has a data input (10) coupled via a capacitor (C1) to a d.c. restoring circuit (C2, Q29 - Q32). The d.c. restoring circuit provides a d.c. reference level upon which the signal is superimposed. A sample and hold circuit (Q1, Q2, C1) is arranged to sample the data signal and provide a voltage related to the upper and lower peak value. A divider (R16-R19) is coupled between the d.c. reference level and the voltage related to the upper and lower peak value and provides intermediate output voltages (DU, DL, B) relating to duo-binary and/or binary level for determining the slicing levels. <IMAGE></p> |
