发明名称 |
Plural cache architecture for real time multitasking |
摘要 |
In a data processor, when there is any cache memory not being activated after the whole data processor has been activated, a signal is delivered to a bus driver and then a data processing unit is connected to a system bus. During the period from when the whole data processor has been activated to when all the cache memories start to be activated, the data processing unit is connected to the system bus so that data can be transmitted/received between the data processing unit and peripheral devices.
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申请公布号 |
US5142671(A) |
申请公布日期 |
1992.08.25 |
申请号 |
US19890434046 |
申请日期 |
1989.11.09 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ISHIDA, ITSUKO;HATA, MASAYUKI;YAMADA, AKIRA |
分类号 |
G06F12/08;G06F13/36 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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