| 摘要 |
PURPOSE:To stably obtain a timing signal for phase comparison of a reference clock against any disturbance on a reference input clock and a VCO output after the PLL enters the locking state. CONSTITUTION:OR circuits 91, 92 OR input reference clocks (1)64kHz, (2)8kHz and timing signals (3), (4) of frequency division outputs of a voltage controlled oscillator VCO 5 and its OR output resets phase comparators 1, 2. Thus, even when the output of the VCO 5 is synchronized with the reference input clocks (1), (2), a phase lead control component and a phase lag control component are provided by the same quantity from the phase comparators 1, 2 to an integration circuit 4. |
