发明名称 |
MEMORY BANK ADDRESS CALCULATION WITH REDUCED INSTRUCTION EXECUTION CYCLES |
摘要 |
A microcomputer in which a higher address must be corrected according to a carry or borrow signal generated during address computation for memory reference based on each addressing mode. The microcomputer is provided with a databank register for holding the higher address and a temporary register for storing a value obtained by incrementing or decrementing by one digit the contents of the data bank register so that the higher order address may be corrected with neither increase in the number of instruction executing cycles nor loss of the memory area continuity.
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申请公布号 |
US5142636(A) |
申请公布日期 |
1992.08.25 |
申请号 |
US19910678894 |
申请日期 |
1991.03.28 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ITOH, SAKAE |
分类号 |
G06F9/355;(IPC1-7):G06F9/32 |
主分类号 |
G06F9/355 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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