发明名称 LSI CHIP DESIGN SYSTEM
摘要 PURPOSE:To execute the layout of an internal circuit on a chip while executing the assembling inspection of plural LSI packages respectively mounting chips at the time of designing the chip. CONSTITUTION:While executing the layout of an internal circuit on a chip by a chip layout part 13 having a general chip layout CAD system, plural LSI packages to be mounted can be selected from an LSI package data base 11 by an LSI package selection part 12, and when an assembling state is changed in the chip layout by specifying electric connection among the chip and the selected LSI packages, the assembling inspection of the plural selected LSI packages can be instantaneously executed by an assembling checking part 15 and the checked result is informed.
申请公布号 JPH04236668(A) 申请公布日期 1992.08.25
申请号 JP19910004927 申请日期 1991.01.21
申请人 NEC CORP 发明人 TOMOTA HIROSHI
分类号 H01L21/52;G06F17/50;H01L21/82 主分类号 H01L21/52
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